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Shantanu Mehta


Shantanu Mehta pursued his secondary and higher secondary education from University of Pune, India in 2005 and 2007 respectively. He graduated with a B.E. in Electronics and Telecommunications (E&TC) from India in 2011. In 2012 he completed his M.Tech from VIT, India in Very Large Scale Integration (VLSI) Design.
Since, January 2015 he has been with Circuits and Systems Research Centre (CSRC) based in University of Limerick pursuing his PhD in Analog-Mixed-Signal Design. For his doctoral thesis, he is working on current-steering D/A converter technology, understanding the fundamentals of mismatch, noise and distortion performance. He is looking at error compensation techniques to alleviate error performance in RF-DAC designs. From November 2016 to July 2017 he worked with Analog Devices, Limerick as a Design Engineer Intern in an automotive group.

Research Interests

Analog Mixed-Signal Integrated Circuit Design, Low power and high-speed D/A & A/D Converters, Digital Signal processing, Sigma-Delta A/D and D/A converters, Dynamic element matching techniques.

Professional Activities


  • 2019 Member, IEEE


  • 2016 Analog Devices, Ireland - Analog Design Engineer


  • 2014 Vellore Institute of India, India - M.Tech
  • 2011 Walchand Institute of Technology, India - B.Eng.


  • English
  • Hindi


Conference Publication

Other Journal


Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
S. Mehta, D. O'Hare, V. O'Brien, E. Thompson, B. Mullane
IEEE Open Journal of Circuits and Systems DOI: 10.1109/OJCAS.2020.2994838