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Home | Generating VHDL-AMS models of digital-to-analogue converters from MATLAB (R)/SIMULINK (R)
Generating VHDL-AMS models of digital-to-analogue converters from MATLAB (R)/SIMULINK (R)
da Silva, ACR,Grout, I,Ryan, J,O'Shea, T,Ernst, LJ,Zhang, GQ,Rodgers, P,Meuwissen, M,Marco, S,VanDriel, WD,DeSaintLeger, O
(2007)
Generating VHDL-AMS models of digital-to-analogue converters from MATLAB (R)/SIMULINK (R) in Eurosime 2007: Thermal, Mechanical And Multi-Physics Simulation And Experiments In Micro-Electronics And Micro-Systems, Proceedings