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Dr. Shantanu Mehta


Shantanu Mehta pursued his secondary and higher secondary education from University of Pune, India in 2005 and 2007 respectively. He graduated with a B.E. in Electronics and Telecommunication from University of Solapur, India in 2011. In 2012 he joined Vellore Institute of Technology, India to pursue his masters in VLSI (Very Large Scale Integration) Design. During his masters he worked on several projects in the areas of Analog/Mixed Signal Design and High-speed DSP(Digital Signal Processing) applications. Since, January 2015 he is working as a PhD Researcher with CSRC group based in University of Limerick. From Nov 2016 to July 2017, he worked as a Design Engineer Intern with Analog Devices based in Limerick and designed AAF(Anti-Aliasing Filter) for an automotive application. His PhD research is primarily focused on low power and high-speed tri-level DEM(Dynamic Element Matching) Techniques for current-steering D/A converters.

Research Interests

High Speed Data Converter Design Techniques (DAC's & ADC's), Analog and Digital Circuit Design, Low power and High Speed DSP Techniques.

Professional Activities


  • 2016 Analog Devices Inc. - Design Engineer Intern


  • 2014 Vellore Institute of Technology, India - Master of Technology
  • 2011 Walchand Institute of Technology, India - Bachelor of Engineering/Science


  • Member, IEEE


  • English
  • Hindi


Other Journals


High Speed and Efficient 4-Tap FIR Filter Design Using Modified ETA and Multipliers
Mehta Shantanu Sheetal, Vigneswaran T
(2014) High Speed and Efficient 4-Tap FIR Filter Design Using Modified ETA and Multipliers
In International Journal of Engineering and Technology; pp. 2159-2170