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Home | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
S. Mehta, D. O'Hare, V. O'Brien, E. Thompson, B. Mullane
(2020)
Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs in IEEE Open Journal of Circuits and Systems 10.1109/OJCAS.2020.2994838